Patent Details

Patent ID: CN200910213432.X

A bit line for the memory cell array of the sub-threshold leakage current compensation circuit

Description: A bit line for the memory cell array of the sub-threshold leakage current compensation circuit, a first source terminal of the second transistor are connected to two compensating the power supply voltage, and the gate terminal is connected with the first end of the respective body, a second shielded transmission gate connected to the input terminal of the bit line as a non-terminal end and a bit line, a first drain terminal of the second transistor are connected to two compensating outputs of the first and second shielded transmission gates, respectively, and simultaneously connecting the first, second After the second logical storage capacitor to ground; the first and second shielded transmission gates connected to the body end of each PM tube and the other end of the gate, respectively, as the respective shielded transmission gate control terminal, the first and second shielded transmission gates each other NM body-side end of the tube is connected to the gate, respectively, as the respective complementary shielded transmission gate control terminal, the first and second shielded transmission gate drain terminal of the respective PM and NM source other tube is connected to the other pipe to the respective input terminals , PM and NM drain terminal of the source of the other pipe is connected to the other pipe to the respective output terminals of the first and second pre-charge transistor, a source terminal balance of both the supply voltage, the drain terminals of the bit lines and the bit lines of non-terminal connection; third pre-charge transistor, the source-drain balanced terminal side, respectively, then the non-bit line and bit line; first, second, third, three pre-charge transistor balance gate terminal connected together and to the pre-charge balance signal .

Patent Details:

DOI: G11C7 / 12 (2006.01) I