Patent Details

Patent ID: CN201010102215.6

A structured LDPC code decoding method and apparatus for explicitly storing the system on chip

Description: A structured LDPC code decoding method and an apparatus for explicit storage system on a chip, comprising the steps of: (1) initializing decoding: This initialization process includes the logarithm of the received log-likelihood ratio LLR of a particular storage is stored to the variable node memory blocks, the initialization value of check node memory blocks 0, a pre-set maximum number of iterations; (2) an iterative process: Starting iterations counter Iter, iterate; (3) the output of the decoder Results: When the number of iterations reaches the maximum number of iterations counter Iter decoding operation is completed and the last check node, stopping the decoding and outputting the decoding result; otherwise, go to step (2) to continue the iteration. The decoding apparatus includes a rate reconfigurable storage management controller, decoding and processing array controller unit. The present invention has a simple structure and compact, low cost, easy to operate, can reduce hardware complexity, can support a variety of bit rates and other advantages.

Patent Details:

DOI: H03M13 / 11 (2006.01) I; H04M13 / 00 (2006.01) I